1. Field of the Invention
The present invention relates generally to synchronization of processors, and more particularly to synchronization for control of one processor by another, and still more particularly to synchronization for control of a slave peripheral processor by a host digital processor.
2. Related Art
In recent years, advances in speed and density of integrated circuit devices has led to similar advances in speed and computing power of processor devices. With these advances came a widespread use of processors in numerous applications. As an example of the increased usage of processors, consider the case of peripheral devices. Prior to the advent of low cost, powerful processors, peripheral devices had no processing capacity of their own. Such devices were merely capable of responding to specific instructions from a host processor. With the advances described above, peripheral devices that utilize their own internal processors to achieve enhanced functionality are now available. Such peripheral devices are generally referred to as `smart` peripherals.
When a computing system is provided with a smart peripheral, there is an interaction between the system's host processor and the peripheral's processor that can be described as a typical parallel processing relationship. In a parallel processing system, multiple processors are interfaced in such a manner as to allow each to perform separate computing tasks, wherein each task is a subset of a larger, parent task. In the case of a smart peripheral, the peripheral processor carries out tasks that are a subset of the computing system's task. The host processor is responsible for controlling and synchronizing the activities of the peripheral processor.
Parallel processing systems often employ common memory, common I/O, and common busses that are shared by each of the processors. This too is the case for parallel processing with a peripheral processor. Sharing of such resources among multiple processors requires synchronization of the operations of each processor with respect to every other processor.
With smart peripherals, the host processor may provide a variable number of operations for the peripheral processor to execute. Each of these operations may take a different amount of time to complete. To ensure that system resources and the peripheral processor itself are used in an efficient manner, the peripheral processor is synchronized by the host processor. Without such synchronization, the host processor and the peripheral processor(s) lack the coordination necessary to determine when each can use a portion of the shared memory, or when each may have access to a shared bus.
In conventional parallel processing systems, two general methods are provided for utilizing shared resources. The first method involves interrupts, or polling of a status register, or a combination of these techniques. In polling, to determine when a resource (e.g. a bitmap in shared memory) is no longer required, or when a set of operations is complete, the processor repeatedly reads (polls) a status register. This polling continues until a specific event is detected in the status register indicating the availability of the shared resource. Such polling is done continuously and consumes a large amount of bus bandwidth and requires a substantial amount of processor time. Polling is therefore inefficient. For interrupt systems, a large amount of host processor context switch overhead is involved.
The second method of utilizing shared resources is that of using memory semaphores. Semaphores are flag variable devices that indicate whether a shared resource can be accessed. In semaphore systems a particular message code, or semaphore, is placed in a particular memory location corresponding to the shared resource. The code notifies other processors of the status of the resource. In systems employing memory semaphores, a processor that is waiting on the availability of a particular resource (e.g. a shared memory region) must read the memory location containing the code relating to the status of that resource. If the semaphore indicates the resource is unavailable, the processor enters a wait state. The wait state is punctuated by periodic re-readings of the memory semaphore. The status of repeated waits and reads is known as a "spin lock."
Thus in systems employing semaphore techniques, a specified memory location is used as a flag to indicate that something has completed or needs attention. Semaphores require uninterrupted read-modify-write capabilities in the memory system. The mason an uninterrupted read-modify-write capability is required will now be described. In conventional systems using semaphores to control multiple processors, a type of processor race condition can occur. If a processor is polling a semaphore location to determine resource availability it first reads that location. If the location contains a value indicating that the resource is busy, the processor continues periodic polling. If, however, the location contains a value indicating that the resource is available, the processor must now modify the value and then write the modified value to the semaphore location.
This technique, by itself, leads to problems when multiple processors are polling the semaphore location in the same time frame. If a first processor, as described above, reads the location and proceeds to modify and write the modified value to that location, a second processor must be inhibited from doing the same as soon as the first processor has read the value. If the second processor is not inhibited, both processors will read the value indicating resource availability, both will believe they can access that resource, and both will attempt to modify that value and write to that memory location.
The conventional technique used to overcome this problem is to inhibit processor interruptions during the entire read-modify-write operation. In this manner, if the host (master) is not capable of being interrupted during these operations, a second processor cannot attempt to claim a shared resource that is being claimed by a first processor. Such a system of allowing uninterruptible read-modify-write capabilities leads to inefficient processor utilization.
What is needed, then, is a system and method for controlling the use of slave peripheral processors without inhibiting interrupts to the host processor during the read-modify-write sequence.
What is further needed is an efficient method of determining when a parallel processor no longer requires the use of a shared resource. What is needed is a method that does not continuously poll status registers or require uninterrupted read-modify-write capabilities.